Battery monitoring arrangement having an integrated circuit with logic controller in a battery pack

ABSTRACT

A battery monitoring device of a battery pack configured for powering a cordless power tool may include an integrated circuit connected to a microprocessor of the pack that is external to the integrated circuit, and which is connected to each of N battery cells of the pack. The integrated circuit may be configured to take, singly or sequentially, a sampled reading comprising one of an individual cell voltage or a total pack voltage for all cells in the pack. The sampled reading is filtered in the integrated circuit prior to being read by the microprocessor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/239,286, filed Sep. 30, 2005, which claims priority to U.S.Provisional Application Ser. No. 60/615,201, filed Oct. 4, 2004, theentire contents of which is hereby incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method and device formonitoring battery cells of a battery pack configured for powering acordless power tool, and to a method and arrangement for balancing cellvoltages during a charge.

2. Description of Related Art

Cordless products or devices which use rechargeable batteries areprevalent throughout the workplace and home. Rechargeable batteries maybe used in numerous devices, from computer products and/or housewares topower tools. Nickel-cadmium, nickel-metal-hydride battery and/orlithium-ion cells may be used in these devices. Since the devices use aplurality of battery cells, the battery cells may be ordinarily packagedas battery packs. These battery packs may be coupled with the cordlessdevices so as to secure the pack to the device. The battery pack may beremoved from the cordless device and charged in a battery charger orcharged in the cordless device itself, for example.

SUMMARY OF THE INVENTION

An example embodiment of the present invention is directed to a batterymonitoring device of a battery pack configured for powering a cordlesspower tool. The device may include an integrated circuit connected to amicroprocessor of the pack that is external to the integrated circuit,and connected to each of N battery cells of the pack. The integratedcircuit may be configured to take, singly or sequentially, a sampledreading comprising one of an individual cell voltage or a total packvoltage for all cells in the pack. The sampled reading is filtered inthe integrated circuit prior to being read by the microprocessor.

Another example embodiment of the present invention is directed to amethod of monitoring battery cells of a battery pack that is configuredfor powering a cordless power tool. In the method, a first serial datacommand may be received from a microprocessor of the pack to take avoltage measurement from channels connected to one or more of the cells.The voltage measurement may be embodied as a differential voltage valuemeasured across an individual cell or a differential voltage valuemeasured across all cells to reflect a total pack voltage. The voltagemeasurement may be stored in a capacitor and filtered so that thecapacitor charges up to an average of the differential voltage value fora given cell or across all cells of the pack. A second serial datacommand may be received to connect the capacitor to a buffer amplifierso that the microprocessor can read the average voltage value off thecapacitor.

Another example embodiment of the present invention is directed to anarrangement in a battery pack for balancing cell voltages duringcharging of a plurality of cells of the pack. The arrangement mayinclude a microprocessor and an integrated circuit in operativecommunication with the microprocessor and connected to each of thecells. The microprocessor may direct the integrated circuit toperiodically measure, throughout the duration of charging, the cellvoltage across each cell of the pack and the total pack voltage in asequential manner. The integrated circuit communicates the measuredindividual cell voltage and a current average cell voltage for all cellsto the microprocessor. The measured total pack voltage is automaticallydivided by the number of cells within the integrated circuit todetermine the current average cell voltage. The microprocessor controlsbalancing of each of the cell voltages during the charge based on eachmeasured individual cell voltage and the determined current average cellvoltage.

Another example embodiment of the present invention is directed to amethod of adaptively balancing cell voltages of a plurality of cells ina battery pack during charging of the battery pack. The method includescontinuously monitoring cell voltages for each cell in the pack in asequential manner, and detecting a voltage differential for one or morecells. The voltage differential may be represented as the difference agiven measure cell voltage exceeds a current average cell voltage valuecalculated from the continuously monitoring step. Cell voltages may bebalanced during the charge by discharging those cells having a detectedvoltage differential, until a measured cell voltage for the dischargingcell has dropped to equal the average cell voltage.

Another example embodiment of the present invention is directed to abattery pack configured to monitor voltages of cells therein, thebattery pack operatively attachable to a cordless power tool. Thebattery pack includes a microprocessor and an integrated circuit inoperative communication with the microprocessor for monitoring cellvoltages of at least N individual cells and total pack voltage duringdischarge of the pack, based on commands received from themicroprocessor. The battery pack includes a motor control semiconductordevice operatively controlled by the microprocessor. As the battery packis engaged to a cordless power tool, and upon an initial actuation of atrigger of the power tool, the microprocessor directs the integratedcircuit to sequentially measure the individual cell voltages of all thecells. The microprocessor may energize the motor control semiconductordevice to enable battery current to flow to a motor of the power tool,if the determined individual cell voltages are acceptable as compared toa given voltage threshold.

BRIEF DESCRIPTION OF THE DRAWINGS

The example embodiments of the present invention will become more fullyunderstood from the detailed description given herein below and theaccompanying drawings, wherein like elements are represented by likereference numerals, which are given by way of illustration only and thusare not limitative of the example embodiments of the present invention.

FIG. 1 illustrates a block diagram of a arrangement for monitory batteryparameters in accordance with an example embodiment of the presentinvention.

FIG. 2 is a flow diagram illustrating data flow between themicrocontroller and ASIC of FIG. 1, in accordance with an exampleembodiment of the present invention.

FIG. 3 is a block diagram illustrating components and terminals of anexample battery pack in accordance with an example embodiment of thepresent invention.

FIG. 4 is a block diagram illustrating components and connection betweenan example battery pack and an example battery charger in accordancewith an example embodiment of the present invention.

FIG. 5 is a block diagram illustrating components and connectionsbetween an example battery pack and an example power tool in accordancewith an example embodiment of the present invention.

FIGS. 6-8 illustrate example cordless power tools configured to bepowered from the example battery pack in accordance with the presentinvention.

DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS

FIG. 1 illustrates a block diagram of an arrangement for monitoringbattery parameters in accordance with an example embodiment of thepresent invention. The battery monitoring arrangement 200 in FIG. 1 maybe configured for sensing certain battery parameters of a battery pack,such as individual cell voltages and/or total stack voltage of the pack.

The battery monitoring arrangement 200 may be part of a removable powersource adapted to power a system of cordless power tools. Examplecordless power tools may include a circular power saw 10 (FIG. 6), areciprocating saw 20 (FIG. 7) and a drill 30 (FIG. 8). The tools 10, 20and 30 each may include a conventional DC motor (not shown) adapted tobe powered by a power source having a given nominal voltage rating. Inthe example embodiments, the tools 10, 20 and 30 may be driven by aremovable power source having a nominal voltage rating of at least 18volts. It will become evident to those skilled that the presentinvention is not limited to the particular types of tools shown in thedrawings nor to specific voltages recited as examples below. In thisregard, the teachings of the present invention may be applicable tovirtually any type of cordless power tool and any supply voltage.

The removable power source may be embodied as a battery pack 40 having ahousing which includes battery monitoring arrangement 200 therein formonitoring battery parameters. The battery pack may be a rechargeablebattery pack 40. Battery pack 40 may include a plurality of batterycells within its housing that are connected in series, and/or aplurality of serially-connected strings of cells, in which the stringsare in parallel with one another.

For purposes of describing the example embodiments, battery pack 40 maybe composed of a plurality of cells having a lithium-ion cell chemistry.As the example embodiments are directed to a battery monitoringarrangement 200 for use in a cordless power tool environment, whichrequires power sources with much higher voltage ratings thanconventional low voltage devices using Li-ion battery technology, (suchas laptop computers and cellular phones) the nominal voltage rating ofthe battery pack 40 may be at least 18V.

However, battery pack 40 may be composed of cells of anotherlithium-based chemistry, such as lithium metal or lithium polymer, orother chemistry such as nickel cadmium (NiCd), nickel metal hydride(NiMH) and lead-acid, for example, in terms of the chemistry makeup ofindividual cells, electrodes and electrolyte of the pack 40.

Referring now to FIG. 1, the arrangement 200 may be part of battery pack40 and includes a battery monitoring device 220. Device 220, which inFIG. 1 is shown as a single integrated circuit (IC) 220, interfacesand/or is in operative communication with a pack controller 250 withinthe housing of battery pack 40, and a stack 210 of up to N batterycells. The pack controller may be referred to hereafter as a digitalmicroprocessor 250. In an example, N may be at least 5 cells, with stack210 being comprised of a number of cells in a range of about 5 to 20battery cells. In other examples, the stack 210 may be embodied by aseven (7) cell configuration, a fourteen (14) cell configuration and/orthe illustrative ten (10) cell configuration shown in FIG. 1. In each ofthe previous examples, the battery pack 40 may be capable of providingan output voltage to its attached cordless power tool in a range ofabout 18-40 volts. In an additional example, the battery pack 40 may beconfigured within a range of 7-14 cells to realize a pack voltagebetween about 25 to 36 volts. These voltages and cell counts for pack 40are merely exemplary, the present invention is not so limited to theabove cell configuration and/or voltage ratings.

As will be explained hereafter, by using digital communications, such asthree-wire serial communication, for example, the microprocessor 250 maysend and receive commands to and from IC 220. As will be explained infurther detail below, IC 220 may be directed, via one or more serialdata commands sent over serial data lines 215 by microprocessor 250, tosequentially sample channels corresponding to the battery cells of stack210 and to level shift each of the sampled readings to a buffered outputat buffer amp 227 to the microprocessor 250 via an A/D pin so as tomeasure the sampled reading. As will be seen below, IC 220 is alsocapable of discharging individual or multiple cells through internalbalancing semiconductor devices, as commanded by the microprocessor 250.

In FIG. 1, the block diagram of arrangement 200 may represent only aportion of the internal circuit makeup of the battery pack 40 shown inany of FIGS. 6-8. The battery pack 40 may include additionalfunctionality or components such as other microprocessors orcontrollers, a current sensor, a pack temperature sensor, packidentification component(s), current limiting device(s), otherprotection circuits such as fuses and/or other internal components forexample, which are not shown herein for reasons of clarity.

Although in FIG. 1, IC 220 is shown as a single application specificintegrated circuit (ASIC), the battery monitoring device may be furtherembodied in hardware or software as a digital microcontroller, amicroprocessor, an analog circuit, a digital signal processor or by oneor more digital ICs such as multiple application specific integratedcircuits (ASICs), for example.

The pack controller in FIG. 1 hereafter is described as a digitalmicroprocessor 250, and may be embodied as a Pentium® processor byIntel®. Alternatively, this controller may be configured as an analogcircuit, a digital signal processor, and/or embodied as one or moredigital ICs such as application specific integrated circuits (ASICs),etc., for example. In the example embodiments and as describedhereafter, the microprocessor 250 is external to and not part of IC 220,as microprocessor 250 resides separately within the housing of thebattery pack 40, in communication with IC 220 via a series of serialdata lines 215.

Each of the example battery cells in stack 210 has a correspondingselectable channel, Ch1 to Ch10. The channels represent pins of the IC220. For example, Ch0 is an ASIC pin connected to the negative side ofits cell (cell 1) on the low side or bottom of battery stack 210, CH1 isthe pin connected to the positive side of cell 1 and the negative sideof cell 2, etc. The pins labeled FET1 through FET 10 represent pins ofcorresponding semiconductor devices (field effect transistors FET1through FET 10) and are connected to the positive sides of cells 1-10.The function of FETs 1-10 will be explained in further detail below. IC220 is operatively connected to corresponding channels of each cell inthe stack 210. Each channel thus may be configured to provide a channelinput from its corresponding cell to the IC 220.

Arrangement 200 may include a voltage regulator 230 that supplies aninternal control voltage (low voltage Vcc) to the IC 220 andmicroprocessor 250. For example, when the trigger switch 205 of anattached power tool is closed, the stack 210 of battery cells (or acharger) may supply a given input voltage Vin to the regulator 230,which, in turn, supplies a stepped down internal control voltage Vcc tothe IC 220 and microprocessor 250. The Vcc supplied to the IC 220 may befiltered, such as by including filtering circuitry 231. A regulatorbypass transistor 260 may be provided to dissipate power, so that poweris not dissipated in the regulator 230. The PSC signal from the voltageregulator 230 controls the base current in transistor 260 so that VCCremains in a desired stable range, as is known. The voltage reference(Vref) provided by regulator 230 to microprocessor 250 is a constantVref for the A/D converter (not shown) in the microprocessor 250.

Accordingly, IC 220 is intended to interface microprocessor 250 and astack 210 of up to N battery cells. Using three-wire serialcommunication, for example, the microprocessor 250 may send and receivecommands to and from the IC 220. The IC 220 device is connected to thestack 210 of battery cells and has access to each cell voltage. Powerfor the IC 220 may be supplied from a low voltage Vcc pin and a highvoltage Vin pin or Vin power terminal. The Vin power terminal may beseparate from the Ch10 terminal. The Vin power terminal may be filtered,such as by including filtering circuitry 212 and thus, may be subject toless intense voltage fluctuations. IC 220 may also receive external Vccpower on the Vcc pin if the PSC pin is left open. By reading the voltageacross Rsense, IC 220 can limit the current through the bypasstransistor 260. Once Vcc is established, the IC 220 creates atemperature-stabilized Vref for the A/D converter in the microprocessor250.

Data communication may be embodied via serial transmission using asuitable interface. IC 220 may thus include a logic controller 222 fordata communications between the microprocessor 250 and IC 220. As anexample, logic controller 222 may be embodied as a Serial PeripheralInterface (SPI) logic controller.

In general, a SPI may be used for a synchronous serial communicationbetween a host processor, such as the microprocessor 250 and peripheralssuch as the logic controller 222 in the IC 220. The SPI typically isconfigured with two control lines, chip select (CS) and clock (SCK) andtwo data lines, serial data in (SDI) and serial data out (SDO). Althoughonly one direction is shown for SDI and SDO pins, both themicroprocessor 250 and IC 220 have respective SDI and SDO pins. Dataflow thus may be transmitted from the SDO pin of the controller 250 tothe SDI pin of the IC 220, and/or from SDO pin of the IC 220 to the SDIpin of the controller 250, as is known. With the CS pin, thecorresponding peripheral device is selected. This pin is primarilyactive-low. In an unselected state, the SDO lines are in ahigh-impedance state (hi-Z) and therefore inactive. The SCK line isbrought to the device (IC 220) whether it is selected or not. The SCKsignal serves as synchronization of the data communication.

In general SPI operation, a master device (microprocessor 250) decideswith which peripheral device (i.e., IC 220) it wants to communicate. Themaster device provides the clock signal SCK and determines the state ofthe chip select (CS) lines, i.e. it activates the slave (IC 220) itwants to communicate with. CS and SCK are therefore outputs. The slavedevice (such as the IC 220) receives the SCK and CS select from asinputs. This means there is one master, while the number of slaves isonly limited by the number of chip selects. If a SPI device is notselected, its data output (SDO) goes into a high-impedance state (hi-Z),so that it does not interfere with currently selected devices.

An SPI device can be a simple shift register up to an independentsubsystem. The length of the shift registers may differ from device todevice. Normally the shift registers may be 8-Bit or integral multiplesof it. There also exist shift registers with an odd number of bits. Forexample, two cascaded 9-Bit EEPROMs can store 18-Bit data.

Although serial communication between the microprocessor 250 and IC 220described herein is based on the example SPI logic controller 222, it isevident to those of skill in the art that the arrangement could achievedesirable serial communication between devices using Inter IC (I²C)and/or Universal Asynchronous Receiver/Transmitter (USART) interfacesand/or chip components in place of the SPI logic controller of FIG. 1.

SPI logic controller 222, in addition to being the interface forcommunications between microprocessor 250 and IC 220, is in operativecommunication with various additional components of IC 220. For example,SPI logic controller 222 may output control signals (based on commandsreceived from microprocessor 250) to drive gate drive circuitry 224and/or a switch matrix 225. The component arrangement that comprisesgate drive circuitry 224 is known in the art and thus is not describedherein for reasons of brevity. In an example, switch matrix 225 may beembodied as an analog multiplexer. The function of the switch matrix 225is to select given channel(s) for sampling and acquisition of batterypack parameters based on the control signal(s) received from SPI logiccontroller 222 (which in turn correspond to the given data commandreceived from microprocessor 250).

Based on a received command from microprocessor 250, SPI logiccontroller 222 may also output control signals to drive the gate drivecircuitry 224, so as to switch a given semiconductor device (FET) insemiconductor device stack 228 to either ON or OFF. These FETs may becontrolled, via SPI logic controller 222 and gate drive circuitry 224,so as to selectively permit discharge of a given cell (or not), henceFETs 1 to 10 may be occasionally referred to as “balance FETs”. Eachchannel may be connected with a corresponding balance FET in stack 228.The control and operation of the balance FETs in stack 228 will beexplained in further detail below.

As another example, based on a received command from microprocessor 250,SPI logic controller 222 may output control signals directing the switchmatrix 225 to monitor a battery parameter of a given channel, and/or tosequentially and/or switch from channel to channel over a given duration(or continuously) to monitor certain battery parameters of each the Ncells, including total battery stack voltage (e.g., total battery packvoltage). Accordingly, and based on the digital data command receivedfrom microprocessor 250, switch matrix 225 may be directed (via controlsignals from SPI logic controller 222) to select channels for monitoringvarious battery parameters, including, but not limited to: cell voltageof a selected individual cell, total pack voltage (i.e. total batterystack voltage), internal or external voltage references, packtemperatures, and/or monitoring a ground to ground connection for errorcorrection, etc.

In general, and based on the command received, the switch matrix 225selects designated channels to sample the battery parameter of interest.Although sample and acquisition processes will be explained in moredetail below, in general, the sampled reading or parameter of the cellbeing sampled (in this example a cell voltage value) is first stored asan average voltage value onto an external capacitor, shown as C203 inFIG. 1. The capacitor 203 is external to IC 220 to allow the circuitdesigner flexibility in sizing the filter frequency. The output ofswitch matrix 225 (which is a differential voltage value measured fromtwo channels, one on either side of the given cell of interest as shownin FIG. 1 or Table 1) is digitally filtered through an RC filteringcircuit formed by capacitor C203 and internal resistor R1 in FIG. 1, ascapacitor C203 is being charged.

The filtering desirably removes high frequency noise (which may be dueto the discharge of the battery pack, or from the switch matrix 225).Due to filtering, the signal being stored as C203 charges up is anaverage voltage value across the cell of interest (e.g., the average ofthe differential cell voltage taken from the two channels bracketing thecell). This may provide a more accurate measurement to themicroprocessor 250's A/D converter, for example.

Thus, with filtering provided by the RC filtering circuit (R1 and C203),C203 charges up to the average voltage across the cell. After a softwarecontrolled delay to allow C203 to charge, and based on another datacommand received from microprocessor 250, the capacitor C203 isdisconnected from switch matrix 225 and connected to buffer amp 227.Buffer amp 227 receives the stored average voltage value from C203, ananalog voltage signal. Buffer amp 227 is provided so that capacitor C203does not bleed off while the microprocessor 250 is taking themeasurement. The Vout sent (via buffer amp 227) to the A/D converter inthe microprocessor 250 is a much cleaner analog signal representation ofthe measured cell voltage, as compared to what would be present withoutfiltering.

As shown in FIG. 1, the output of the buffer-amp 227, Vout, may be fedthrough an optional external filter or conditioning circuit 233 to theA/D converter within microprocessor 250 for analog to digital conversioninto a digital voltage value. No offset correction to the digitalvoltage value of Vout is required to be performed in microprocessor 250in order to detect (measure) an accurate cell voltage. Because C203 istied to ground via switch SW2 DB2, as shown in FIG. 1, the copy of theaverage voltage of the selected cell on C203 is now ground referencedand ready for reading, as Vout from buffer-amp 227, by the A/D converterin microprocessor 250.

Thus, various 8-bit commands sent by the microprocessor 250 through theSDI line may direct the IC 220 to take a measurement and output theanalog measurement value through the Vout pin via a conditioning circuit233 to the microprocessor 250 digital conversion and detection(measurement). This enables the microprocessor 250 to read anyindividual cell voltage within the stack 210 without having to performtwo or more single-ended measurements and/or a digital subtraction oroffset correction to determine (measure) the cell voltage.

Accordingly, to sample a battery pack parameter such as an individualcell voltage, and referring to FIG. 1, a command is sent from themicroprocessor 250 to the SPI logic controller 222. SPI logic controller222 in turn sends control signals to close switch matrix 225 and selectthe given channel to DB1 and DB2 pins of IC220, and to align switchpositions (SHUNT of OPEN) for sampling, e.g., switches SW2 DB1, SW2 DB2,DB1SELGND and DB1SELGND all have logic low states (=0) or OPEN, andswitch SW1=1 (SHUNT) to take the sampled reading as capacitor C203 ischarged through resistor R1.

After a software controlled delay (which may be a few milliseconds), theSPI logic controller 222 may receive another command from microprocessor250 to open switch matrix 225, open switch SW1 and shut each of switchesSW2DB1, SW2DB2, DB1SELGND and DB1SELGND (logic high=1). This connectsC203 to buffer amp 227 for output as Vout, e.g., an analog averagevoltage value of the cell, to the microprocessor 250

Other commands may enable and/or disable a given balance FET on a givenchannel where the intent is to drain a specific current which is set byexternal resistors 213. As will be shown below in further detail, acommand may be sent by microprocessor 250 to direct the IC 220 to readthe total stack voltage with an automatic divide by ten on the output ofswitch matrix 225.

Table 1 provides an example list of 8-bit commands that may betransmitted by microprocessor 250 over the SDI line to the IC 220.Across the top row of Table 1, there is shown the 8-bit command (DataLine), what is selected to the DB1 and DB2 pins of the IC 220, theswitch positions for switches SW1, SW2 (DB1 and DB2), SW3, SW4 and SW5,and the action of a given FET in FET stack 228.

TABLE I Example Command Structure FET Data Line DB1 DB2 S1 S2 S3 S4 S5Action 0000 0000 Gnd Gnd Open Shunt Open Open Open No Change 0000 0001Ch1 Ch0 Shunt Open Open Open Open No Change 0000 0010 Ch2 Ch1 Shunt OpenOpen Open Open No Change 0000 0011 Ch3 Ch2 Shunt Open Open Open Open NoChange 0000 0100 Ch4 Ch3 Shunt Open Open Open Open No Change 0000 0101Ch5 Ch4 Shunt Open Open Open Open No Change 0000 0110 Ch6 Ch5 Shunt OpenOpen Open Open No Change 0000 0111 Ch7 Ch6 Shunt Open Open Open Open NoChange 0000 1000 Ch8 Ch7 Shunt Open Open Open Open No Change 0000 1001Ch9 Ch8 Shunt Open Open Open Open No Change 0000 1010 Ch10 Ch9 ShuntOpen Open Open Open No Change 0000 1011 Vcc Gnd Open Open Open Open OpenNo Change 0000 1100 Vref Gnd Open Open Open Open Open No Change 00001101 Gnd Gnd Open Open Open Shunt Open No Change 0000 1110 Gnd Gnd OpenOpen Open Open Shunt No Change 0000 1111 Ch10 Ch0 Shunt Shunt Shunt OpenOpen No Change 0010 0001 Ch1 Ch0 Shunt Open Open Open Open FET 1 On 00100010 Ch2 Ch1 Shunt Open Open Open Open FET 2 On 0010 0011 Ch3 Ch2 ShuntOpen Open Open Open FET 3 On 0010 0100 Ch4 Ch3 Shunt Open Open Open OpenFET 4 On 0010 0101 Ch5 Ch4 Shunt Open Open Open Open FET 5 On 0010 0110Ch6 Ch5 Shunt Open Open Open Open FET 6 On 0010 0111 Ch7 Ch6 Shunt OpenOpen Open Open FET 7 On 0010 1000 Ch8 Ch7 Shunt Open Open Open Open FET8 On 0010 1001 Ch9 Ch8 Shunt Open Open Open Open FET 9 On 0010 1010 Ch10Ch9 Shunt Open Open Open Open FET 10 On 0010 1111 Ch10 Ch0 Shunt ShuntShunt Open Open All FETs On 0011 0001 Ch1 Ch0 Shunt Open Open Open OpenFET 1 Off 0011 0010 Ch2 Ch1 Shunt Open Open Open Open FET 2 Off 00110011 Ch3 Ch2 Shunt Open Open Open Open FET 3 Off 0011 0100 Ch4 Ch3 ShuntOpen Open Open Open FET 4 Off 0011 0101 Ch5 Ch4 Shunt Open Open OpenOpen FET 5 Off 0011 0110 Ch6 Ch5 Shunt Open Open Open Open FET 6 Off0011 0111 Ch7 Ch6 Shunt Open Open Open Open FET 7 Off 0011 1000 Ch8 Ch7Shunt Open Open Open Open FET 8 Off 0011 1001 Ch9 Ch8 Shunt Open OpenOpen Open FET 9 Off 0011 1010 Ch10 Ch9 Shunt Open Open Open Open FET 10Off 0011 1011 “Wake up” Shunt Shunt Open Open Open All FETs Off 00111110 Sleep Mode Open Open Open Open Open All FETs Off 0011 1111 Ch10 Ch0Shunt Shunt Shunt Open Open All FETs Off

As shown in FIG. 1, there is provided an auxiliary circuit (consistingof switches DB1SELVcc, DB1SELVref, DB1SELGND and DB2SELGND) for anexternal device that is connectable to pins DB1 and DB2. In an example,the external device may be a high voltage differential amplifier, whichcould be added to replace the switch-capacitor arrangement of switchesSW1-SW5 and C203 (e.g., switch-capacitor arrangement) in IC 220, or toprovide a back-up battery monitoring means if the switch-capacitorarrangement fails. Accordingly, the external differential amplifierwould be connected to the output of the switch matrix 225 to providedifferential voltage measurements from the directly to the A/D converterof the micro 250?, clarify].

By using command “0000 1101” and reading the voltage on Vout, themicroprocessor 250 can determine whether or not the external amplifieris connected to DB1 and DB2. In an example, if an external device isused, the voltage reading will be ground potential (GND). If the IC220is used, then the voltage reading will be 5 volts. If the externalamplifier is used, the command “0000 0000” is not used for acquisition.

Individual Cell Voltage Measurements

Referring to Table 1, and in an example, assume a command “0000 0111” issent from the microprocessor 250 to the IC 220, which is a command formeasuring the cell voltage of cell 6 between channels Ch6 and Ch7. Ascan be seen from Table 1, this command made no changes to the status ofany of the balance FETs in stack 228. The command is processed by SPIlogic controller 222 and returned back to the microprocessor 250 duringthe next byte transfer on the SDO line for verification. This is becauseimmediately following the original command, the microprocessor 250continues to toggle the SCK line, while the logic controller 222 sendsthe original command back for verification.

Once read, the SPI logic controller 222 controls the switch matrix 225to select Ch7 to the DB1 pin and to select Ch6 to the DB2 pin, so as tosample a differential voltage representative of the cell voltage at cell6. At the same time, SW1 closes to start charging capacitor C203 acrosspins DB1 and DB2, via the RC network formed by R1 and C203. Accordingly,due to the filtering of the RC network, capacitor C203 stores an averageof the differential voltage for cell 6, rather than the immediatedifferential voltage for cell 6 which could fluctuate wildly ascharge/discharge currents change.

After a software controlled delay, the microprocessor sends a secondcommand 0000 0000. As shown in Table 1, this command opens switch matrix225 and switch SW1 and shuts each of switches SW2DB1, SW2DB2, DB1SELGNDand DB1SELGND (logic high=1). This connects C203 to buffer amp 227 tofeed Vout to the microprocessor 250's A/D converter. The remaining cellsof stack 210 can be read the same way.

Total Stack Voltage Measurement

A command may be used by microprocessor to read total stack voltage. Tomeasure total stack voltage, microprocessor 250 sends the command “00001111” to the IC 220, which is a command for measuring the total stackvoltage between CH0 and Ch10. The command is processed by SPI logiccontroller 222 and returned back to the microprocessor 250 during thenext byte transfer on the SDO line for verification. As shown in Table 1and with reference to FIG. 1, the SPI logic controller 222 controls theswitch matrix 225 to select Ch10 to the DB1 pin and to select Ch0 to theDB2 pin, so as to sample a differential voltage representing the totalstack voltage of the battery pack. At the same time, switches SW1, SW2and SW3 close to start charging capacitor C203 across pins DB1 and DB2,through a voltage divider circuit formed by R1 and R2 that chargescapacitor to the average voltage of the stack at a 10:1 ratio. The 10:1ratio is thus set by the values of R1 and R2.

The voltage value being stored on capacitor C203 is filtered through theRC network formed by R1 and C203 to obtain an average voltage value ofthe total stack voltage. After a software controlled delay, themicroprocessor 250 may send command 0000 0000 to connect C203 to bufferamp 227 to feed Vout to the microprocessor 250's A/D converter. However,since switch SW2 is shut during sample and acquisition of total stackvoltage, the microprocessor 250's A/D can continuously measure totalstack voltage.

The switch matrix 225 can change to any channel from any other channelwithout shorting the cell voltages, which ordinarily may cause ashoot-through condition. Shoot-through is a condition that normallyoccurs during a transition of a switch from one connection to another.If a switch were to make contact with one branch of a circuit beforebreaking contact with a second branch, current could flow from the firstbranch to the second branch. This is an undesirable condition and thusmost switches are designed with a “break before make” contact system.The output of the switch matrix 225 is thus filtered by the RC circuitbefore entering the buffer-amp 227.

In FIG. 1, the CS pin is the Chip Select. When pulled low, the SPI logiccontroller 222 will function normally. When pulled high, the SPI logiccontroller 222 send and receive logic is reset. This function is usefulfor packet/byte synchronization to keep the IC 220 bit countersynchronous with the master clock. The SDO pin may be set to tri-stateduring this reset, as is known.

IC 220 may include a SLEEP pin, shown generally at 236. Referring toFIG. 1 and Table 1, a SLEEP command 0011 1110, when given, will cause IC220 to be switched into a low-power sleep mode. Thus, as the SLEEP pin236 is pulled low, the IC 220 is switched into a low-power sleep mode.All FET's in stack 228 are disabled and the V_(out) is disabled andswitched to a high Z state. SPI logic of logic controller 222 is alsodisabled during sleep mode and the SDO pin is set to tri-state.

Also in table 1, a specific “wakeup” command 0011 1011 is provided tobring IC220 out of the sleep mode. When coming out of sleep mode, theSPI logic is reset regardless of the status of the CS pin. The balanceFETs in stack 228 are also reset to the “OFF” state upon awakening.

FIG. 2 is a flow diagram illustrating general data flow between themicroprocessor 250 and IC 220 of FIG. 1, in accordance with an exampleembodiment of the present invention. In general, microprocessor 250sends a command (S210) to IC 220 by clocking the SCK pin and sending the8-bit data command on its SDO pin, to be received by the SDI pin of theIC 220. The IC 220 receives the command (S220) and processes the analogoutput. The microprocessor 250 then clocks the SCK pin (S230) to receivethe original command back from the IC 220 over the microprocessor 250'sSDI pin, for verification to the microprocessor 250 that the IC 220understood and implemented the correct command.

If the responding command is different from the original command, themicroprocessor 250's A/D reading (detected or measured value receivedfrom IC 220) is discarded and the original command can be resent. Thistwo byte transfer may be considered excessive for use in electricallyquiet, noise-free environments. In that case, a standard SPI protocolmay be used where hand-shaking is done bit-by-bit instead ofbyte-by-byte. Hand-shaking may be defined as the act of receiving asignal and transmitting it back to the originator for verification.

FIG. 3 is a block diagram illustrating components and terminals of anexample battery pack in accordance with an example embodiment of thepresent invention; and

FIG. 4 is a block diagram illustrating components and connection betweenan example battery pack and an example battery charger in accordancewith an example embodiment of the present invention.

As an implementation example, the arrangement 200 of FIG. 1 is describedin the context of a battery pack 300 as shown in FIGS. 3 and 4. Theblock diagram of battery pack 300 only shows the salient features ofarrangement 200 for purposes of clarity. It may be understood that thebattery pack 300 could have additional sense components in operativecommunication with microprocessor 250, for example, such as a currentsensor, temperature sensor, pack ID device, current limiting device,etc. Hereafter, example features and functions of the IC 220 during anexample charge and discharge cycle are described.

Referring to FIG. 3, battery pack 300 is shown in an inactive state, notconnected to any electrical device. In FIG. 3, four terminals (terminals1-4) are shown. However, the example embodiments should not be limitedto this terminal configuration, as greater or fewer terminals could beincluded, depending on the desired information to be passed between thebattery pack 300 and another connectable electrical device such as apower tool or charger.

The cells of battery stack 210 may be completely dead (0 Volts) in thisexample, with the battery pack 300 sitting idle on a shelf. As shown inFIG. 3, the regulator 230 is not powered, so IC 220 and microprocessor250 are idle and nothing is live. By placing the battery pack 300 intothe charger 400 (FIG. 4), the following events occur:

-   -   (i) The charger 400 supplies a source voltage (here shown as an        example 15 Volts) to the bypass transistor 260 and the Vin pin,        which in turn controls the regulator 230 through the PSC pin.    -   (ii) The regulator 230, in turn, supplies an example 5 Volts        (Vcc) to the microprocessor 250 and IC 220 (low voltage VCC        pins).    -   (iii) The microprocessor 250 resets and begins initializing its        own program parameters. The resets and initialization routines        may be similar to that done by a microprocessor of a PC or        laptop upon start-up, for example, and are not explained in        detail as these procedures are not a focus of the invention.    -   (iv) After initialization, the microprocessor 250 communicates        with the charger 400 (such as with the charge control 420) via        serial communications (not shown for clarity).    -   (v) Microprocessor 250 maintains motor control FET 240 OFF,        since microprocessor 250 has determined that battery pack 300 is        connected to a charger 400 and not a power tool.

Charge Cycle

Referring to FIG. 4, before charging can commence, the A/D readings(values of cell voltages) should be known. The first cell (cell betweenchannels Ch0 and Ch1 in FIG. 1) may be chosen by microprocessor 250sending command 0000 0001 to IC 220. The data may be clocked out to IC220, and after a brief waiting period, a return byte may be clocked backin by the microprocessor 250. The returned byte should match theoriginal command if communication was effective.

While the microprocessor 250 is verifying the returned command, IC220 isputting the first cell's voltage on its DB1 and DB2 pins. The externalcapacitor C203 is charged through the internal resistor R1. After asoftware controlled delay, the microprocessor 250 sends a second command0000 0000 to connect capacitor C203 to buffer amplifier 227 to feed Voutto the microprocessor 250's A/D converter. The remaining cells in stack210 can be read the same way. With the cell voltages known, themicroprocessor 250 in the battery pack 300 may command the charger 400to begin charging.

Dynamic Cell Balancing During Charge

The cells of stack 210 increase in voltage as they are charged. Not allof the cells have the same capacity, so some of the cell voltages arehigher than others. To head off potential overcharge events, the cellsmay be monitored sequentially and continuously as often as needed bymicroprocessor 250, in an effort to detect a voltage differential Forexample, IC 220 may be directed by microprocessor 250 to scan the entirecell stack 210 in about 10 milliseconds, but due to the slow nature ofcharge, longer cycling times could be employed. In any event, themeasuring, evaluating of cell voltages against a threshold and balancingof cells voltages may be repeated throughout the charge as necessary soas to maintain all cell voltages substantially balanced during thecharge.

Each cell may thus be sampled by microprocessor 250 via data commandssent to IC 220, with the detected or measured value stored in anassociated internal or external memory of microprocessor 250. When acomplete scan is taken, for example, the total stack voltage may betaken as an eleventh measurement. This value is scaled or automaticallydivided by 10 in IC 220 via the voltage divider circuit (R1 and R2),such that capacitor C203 charges to an average cell voltage for all thecells. If all the individual cell voltage measurements are added, themeasurements should add up to the average cell voltage times ten. Thisprocedure may be used as an error check on system integrity, forexample.

Moreover, the average cell voltage may also be used as a running,relative reference value, or threshold. This threshold may be todetermine which individual cells have smaller capacity during the chargeand thus are charging faster than the rest. Such smaller capacity cellscould pose a problem if left unattended during charge. As an example,and for lithium-ion cells, an overcharge condition is highly undesirablefor the cell. In the example of FIG. 1, if nine of the cells are at 4volts, and the tenth cell is at 4.2 volts (max voltage), the total stack210 voltage reading is only 40.2 volts. This does not mean it ispermissible to continue charging, since the cell at 4.2 volts would bedamaged if charging were continued. Accordingly, it is desirable toprovide active cell balancing during the charge, so that the voltage ofthe tenth cell (or sixth cell, fourth cell, etc., for example) nevergets any higher in voltage than the average cell voltage value for allcells. This way, all cells in stack 210 reach the peak voltage together.

The microprocessor 250 may thus direct IC 220 to continuously monitoreach of the cells in a sequential manner, taking individual and totalstack voltage measurements so as to detect any voltage differentialbetween the detected individual cell voltage and the average cellvoltage for all cells, which is determined from the automatic divisionof the total stack voltage by 10. In a particular example, and referringto FIG. 1, the detected voltage of cell number 4 (between Ch3 and Ch4)is slightly higher than the reference value, e.g., the determinedaverage cell voltage for all the cells in stack 210. To speed thebalancing of the cells, the microprocessor 250 is able to dynamicallydetect this voltage differential based on a digital comparison betweenthe stored A/D value for the cell (e.g., the detected cell voltage valuefor cell 4) from command 0010 0100 in Table 1, and the stored averagecell voltage A/D value measured by IC 220 when sampling the total stackvoltage, as directed by command 0000 1111).

Arrangement 200 may thus be configured to cycle through all cell voltagemeasurements in about 10 milliseconds, and then may compare the measuredindividual cell A/D values to the measured average cell voltage A/Dvalue to dynamically determine “unbalanced” cells. If the microprocessor250 determines that cell 4 is slightly higher in voltage than theaverage cell voltage of the cells in stack 210, microprocessor 250issues a data command 0010 0100 to the IC 220. This command tells the IC220 to turn the balance FET 4 in semiconductor device stack 228 to theON-state. The cells are all being charged at the same rate except forcell 4, whose charge rate is lowered by the discharge rate with FET 4ON. This allows the other cells to “catch up” to cell 4, as theindividual cell voltage of cell 4 drops so as to meet the average cellvoltage of the stack 210.

So far, determining whether to discharge particular cells during chargein an effort to obtain balanced cell voltages across the pack 300 has bedescribed using the average cell voltage of all cells is stack 210 as abaseline or reference value, (e.g., as a threshold). However,discharging the cell having a maximum differential voltage from theaverage cell voltage of the stack 210 is only one example threshold. Inan alternative, after IC 200 performs each cycle of individual cellvoltage measurements under the direction of the data commands frommicroprocessor 250, microprocessor 250 can issue a command to IC 220 todischarge the highest voltage cell as evident from the individual cellvoltage measurements. In another alternative, based on the voltagemeasurements received in a given (or each) cycle of measurements,microprocessor 250 can issue a command to IC 220 to discharge multiplecells, such as the X highest voltage cell(s), as evident from theindividual cell voltage measurements. In a further alternative,microprocessor 250 may issue a special command to IC 220 to dischargethose cell(s) whose cell voltage measurement exceeds a given voltagethreshold, such as Y multiplied by a minimum voltage for the cell thatmay be set in advance (Y being an integer≧1). These methodologiesrepresent other example types of threshold criteria for discharging oneor more cells in the pack 300 during a charge, in an effort to balancecell voltages evenly during and upon completion of the charge.

Determining Total Stack Voltage of Cell Stack During Charge

As discussed above, and in addition to monitoring the individual cellvoltages, the IC 220 may be commanded to measure the total stack voltageof stack 210 with command 0000 1111. As described earlier, the totalstack 210 voltage may be automatically divided by 10 inside IC 220,which provides an average cell voltage value for cells of the stack 210.The individual A/D readings received by the microprocessor 250 shouldadd up to ten times the stack A/D measurement (i.e., the average cellvoltage used by the microprocessor 250 to determine voltage differentialfor each of the cells in stack 210 in a continuous manner) sent asV_(out) to the A/D pin of the microprocessor 250. This function may bedone as a back up to the cell checking to prevent overcharge.

Additional Example Cell Balancing

As time during the charge elapses, one or more additional cells couldbegin to have a slightly higher voltage than the average cell voltagefor the cells. These additional cell(s) may be discharged by the IC 220concurrently with cell 4, after being commanded to do so by themicroprocessor 250. This may be performed as was described for cell 4above. When scanning the cells that are being discharged, (cell 4 forexample), the most accurate measurement for cell 4 can be made with datacommand 0011 0100. This directs the IC 220 to output the cell 4 voltage,but it also turns off (unlatches) the balance FET for that cell (FET4).With no current being discharged, the voltage of cell 4 is a reasonablysound indicator of its state-of-charge. When finished reading thechannel, the balance FET could be turned back on (if deemed necessary)with command 0010 0100.

Later in the charge, cell 4 voltage has dropped back to the average cellvoltage of the stack 210. The microprocessor 250 determines this as atrigger to stop discharging cell 4. The same command 0011 0100 may besent to IC 220 to measure the cell voltage of cell 4 and un-latch thebalance FET 4. Now cell 4 can receive the full charge current that isbeing received by the remaining cells.

Terminating Charge

Eventually, the cells in stack 210 all reach a voltage where it isdesirable to terminate the charge current. The microprocessor 250 canmake this decision in various ways, which are not discussed here, assuch termination strategies are outside the scope of the invention.Microprocessor 250 may communicate with the charger 400 (i.e., by serialdata communications) so that the charge current is suspended. In thisexample, each cell, when fully charged, may have roughly 4.2 volts ofcharge; thus the voltage at Ch10 is about 42 volts with respect toground. The Vin pin and regulator 230 are still supplied with thecharger 400's 15 volts.

The pack 300 is removed from the charger 400, and may be placed back ina tool-box (or other storage area) to sit for a while. The battery cellsin stack 210 still exert their voltage on the IC 220 pins, but becausethe Vcc pin is not powered and Vin is at zero volts, the IC 220 isshut-down and there is only minimal leakage current drain on the cells.

Discharge Cycle—Battery Pack Operation with Power Tool

FIG. 5 is a block diagram illustrating components and connectionsbetween an example battery pack and an example power tool in accordancewith an example embodiment of the present invention.

In an example, such as when a work day begins, the battery pack 300 maybe placed in a tool 500 as shown in FIG. 5. As soon as the tool triggerswitch 510 is actuated, the cell stack 210 voltage of the pack 300 maybe applied to the regulator 230 and Vin pin of the IC 220. After aninitialization period, the microprocessor 250 realizes that it is in atool (instead of a charger) and checks the cell voltages. If allmeasurements are acceptable, motor control FET 240 is turned on topermit current to tool motor 520. For example, measurements may beacceptable if all cell voltages are above a given voltage level orvoltage threshold, such as a given cut-off voltage below which the cellis in an under-voltage condition.

As during charging, the microprocessor 250 monitors cell voltages duringdischarge of the stack 210. If the trigger switch 510 is released, thevoltage at Vin and the regulated voltage (5V) supplied to themicroprocessor 250 and IC 220 fade away to ground. With no power supply,the microprocessor 250 shuts down and the Motor Control FET 240 isturned off.

When the trigger switch 510 is pulled again, the IC 220 is powered upand the tool motor 520 operation continues. The tool motor 520 will beenabled as long as the trigger switch 510 is pulled and the cellvoltages are greater than a given voltage level or voltage threshold.Once a cell in stack 210 reaches a low voltage threshold such as acut-off voltage, for example, the microprocessor 250 can command theMotor Control FET 240 to turn off. This action saves the cells of stack210 from being over-discharged and prolongs cell life.

If the trigger switch 510 is left on (in certain cases some users maytape the trigger on), the microprocessor 250 will continue to directcommands to IC 220 so as to continuously monitor cell voltages, butmaintains the Motor Control FET 240 in the off state. Once the totalstack voltage has dropped below an example threshold, in this example,this may be 25 volts (because of a small discharge current needed topower the battery circuit), the microprocessor 250 can tell the IC 220to go into sleep mode via the SLEEP pin 236. This action maysubstantially reduce power consumption inside the battery pack 300. TheIC 220 will stay in this mode until the microprocessor 250 is reset. Thebattery pack 300 may be eventually removed from the tool 500 and placedback on the shelf in a discharged state.

The above example charge/discharge cycle illustrates how the IC 220 mayoperate with the microprocessor 250 to prolong cell life. Over-chargeprotection, over-discharge protection and the ability to performadaptive cell-balancing within a battery pack during a charge may all beaccomplished in a battery pack having an arrangement 200 that includesthe IC 220 and microprocessor 250, for example.

The example embodiments of the present invention being thus described,it will be obvious that the same may be varied in many ways. Suchvariations are not to be regarded as departure from the spirit and scopeof the example embodiments of the present invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

1. An arrangement in a battery pack for balancing cell voltages duringcharging of a plurality of cells of the pack, the arrangementcomprising: a microprocessor, and an interface circuit in operativecommunication with the microprocessor and connected to each of thecells, the microprocessor directing the interface circuit toperiodically measure the cell voltage across each cell of the pack andthe total pack voltage, the interface circuit communicating the measuredcell voltage of each cell and at least one of a current average cellvoltage for all cells and the measured total pack voltage to themicroprocessor, wherein one of the interface circuit and themicroprocessor determine the current average cell voltage by dividingthe measured total pack voltage by the number of cells, and, themicroprocessor controlling balancing of each of the cell voltages basedon the measured cell voltage of each cell and the determined currentaverage cell voltage.
 2. The arrangement of claim 1, wherein themicroprocessor controls the balancing of cell voltages by comparing eachmeasured individual cell voltage to the current average cell voltage,and directs the interface circuit to discharge one or more cells whichhave a measured individual cell voltage exceeding the determined currentaverage cell voltage for a given duration during the charge.
 3. Thearrangement of claim 1, wherein the interface circuit includes aplurality of semiconductor devices, each connected to a correspondingcell in the pack, and the interface circuit energizes a semiconductordevice to enable discharging of its corresponding cell for the givenduration, if the corresponding cell has a measured individual cellvoltage greater than the determined current average cell voltage.
 4. Thearrangement of claim 2, wherein the given duration is defined as a timeelapsed until the measured cell voltage of a discharging cell hasdropped to equal the determined current average cell voltage.
 5. Thearrangement of claim 1, wherein the periodic measuring, determining ofaverage cell voltage, and balancing functions are repeated throughoutthe duration of charging to maintain individual cell voltagessubstantially balanced during charging.
 6. A method of adaptivelybalancing cell voltages of a plurality of cells in a battery pack duringcharging of the battery pack, comprising: periodically measuring thecell voltage for each cell in the pack; periodically determining fromsaid measured cell voltages an average cell voltage value, detecting avoltage differential for one or more cells, the voltage differentialcorresponding to a difference between a given measured cell voltage andthe average cell voltage value, and balancing cell voltages duringcharging by discharging those cells which have a measured cell voltagegreater than the average cell voltage value.
 7. The method of claim 6,wherein said balancing step further includes discharging a cell having ameasured cell voltage greater than the average cell voltage value untilthe measured cell voltage for the discharging cell equals the averagecell voltage value.